// Initial exercise to learn Verilog.  See counter.v.
module tb_counter();
   reg clk = 0, reset_n = 1;
   wire [3:0] q;
   counter ctr (reset_n, clk, q);

   always #5 clk <= ~clk;

   initial begin
      $dumpfile("counter.vcd");
      $dumpvars();

      #3 reset_n = 0;           // initially 1, so we get a negedge
      #1 reset_n = 1;
      // Alternative to using the `always` above:
      // for (integer i = 0; i < 40; i = i + 1) begin
      //    #5 clk = ~clk;
      // end
      #200 $finish;
   end
endmodule