// Initial exercise to learn Verilog.  See also tb_counter.v.

// Here we have a four-bit counter with an asynchronous reset line.
module counter(input wire reset_n, input wire clk, output wire [3:0] q);
   reg [3:0] r = 4'b0101;
   assign q = r;

   // Alternative to initializing the reg in the declaration:
   //initial r = 4'b0101; //doesn’t really work: 4'bxxxx;

   always @(posedge clk or negedge reset_n) begin
      if (reset_n === 0) begin
         r <= 0;
      end else begin
         r <= r + 1;
      end
      // Also syntactically valid, but I don’t like it:
      // if (reset_n === 0) r <= 0;
      // else r <= r + 1;
   end
endmodule