@@ See also compressedoops.S.
	.syntax unified
        .thumb
        .thumb_func
        .fpu fpv4-sp-d16
	.cpu cortex-m4

	@@ Suppose you have a compressed OOP in r0 and you want to
	@@ load the first compressed OOP from its object.  The heap
	@@ base pointer is in r4.
        @@ f834 0010  ldrh.w r0, [r4, r0, lsl #1]
	ldrh r0, [r4, r0, lsl #1]

        @@ You can also load the first 32-bit word if it’s 32-bit
	@@ aligned.  (This means bit 0 of r0 is clear.)
        @@ f854 0010  ldr.w r0, [r4, r0, lsl #1]
        ldr r0, [r4, r0, lsl #1]

        @@ But, unlike amd64, you can’t index into the object in a
	@@ single instruction.
        @ ldrh r0, [r4, r0, lsl #1, #4]
        @@ Instead you have to compute the base address in a second
	@@ instruction.
        @@ eb04 0140  add.w r1, r4, r0, lsl #1
        @@ 8888       ldrh  r0, [r1, #4]
	add r1, r4, r0, lsl #1
        ldrh r0, [r1, #4]

        @@ Suppose you want to load six 16-bit fields from compressed
	@@ oop r0.
        add r0, r4, r0, lsl #1
        ldmia r0!, {r1-r3}
        @@ Now you can, for example, add the low 16 bits of r2 (the
	@@ third object field) to the high 16 bits of r1 (the second
	@@ object field).  This leaves the result in the high 16 bits
	@@ of r0 but the correct 16-bit result in its low 16 bits.
        add r0, r2, r1, ror #16